Among semiconductor devices, field effect transistors (FETs) are used widely in various electronic devices.
FIG. 11A shows an example of the structure of a field effect transistor. FIG. 11A is a cross sectional view schematically showing the semiconductor structure of the vertical GaN field effect transistor (hereinafter, referred to as a vertical GaN FET) described in Non-Patent Document 1. As shown in FIG. 11A, in this vertical GaN FET, an i-type GaN layer 101′ is laminated on the upper surface of a sapphire substrate 110. Further, on the upper surface of the i-type GaN layer 101′, a high concentration n-type GaN layer 107 is laminated. On a part of the upper surface of the high concentration n-type GaN layer 107, an n-type GaN layer 102, a p-type GaN layer 103, and an n-type GaN layer 104 are laminated in this order. On parts of the upper surface of the high concentration n-type GaN layer 107 where the aforementioned layers are not laminated, drain electrodes 113 are in ohmic-contact with the high concentration n-type GaN layer 107. On the upper surface of the n-type GaN layer 104, source electrodes 111 are in ohmic-contact with the n-type GaN layer 104. On the upper surface of the high concentration n-type GaN layer 107, the side surfaces of the n-type GaN layer 102, the side surfaces of the p-type GaN layer 103, and the upper surface and the side surfaces of the n-type GaN layer 104, except for the areas where the source electrodes 111 and the drain electrodes 113 are formed, a gate insulation film 121 is laminated. A part of the upper part of the n-type GaN layer 102, a part of the p-type GaN layer 103, and a part of the n-type GaN layer 104 are removed to form an opening portion to be filled. A gate electrode 112 is formed so as to fill the opening portion to be filled via the gate insulation film 121 and is in contact with the n-type GaN layer 102, the p-type GaN layer 103, and the n-type GaN layer 104. This vertical GaN FET can control the concentration of electrons accumulated at the interface between the p-type GaN layer 103 and the gate insulation film 121 by changing a voltage applied to the gate electrode 112. Thereby, the vertical FET can be operated by controlling a current passing between the source electrode 111 and the drain electrode 113.
Further, as for the field effect transistors, many documents are known besides Non-Patent Document 1. Especially, various researches have been conducted into field effect transistors using nitride semiconductors from the viewpoint of improvements in element characteristics and the like. For example, Patent Document 1 describes as follows: “To reduce the chip area and achieve a high withstand voltage operation, in a field effect transistor that uses a nitride compound semiconductor.” (“Problem to be Solved” in the Abstract of Patent Document 1). Patent Document 2 describes as follows: “To achieve a low resistance buffer layer in an electronic device (power electronics device) operated by passing a current through a SiC substrate and nitride semiconductor layers.” (“Problem to be Solved” in the Abstract of Patent Document 2). Patent Document 3 describes as follows: “To provide a nitride semiconductor which has a small resistance of an element and a high operating voltage.” (“Problem to be Solved” in the Abstract of Patent Document 3). Patent Document 4 describes as follows: “To provide a semiconductor device that reduces polarization generated by the lamination of semiconductor layers, has a mesa section for enabling a carrier to move smoothly, and has a low electric resistance.” (“Problem to be Solved” in the Abstract of Patent Document 4).